`timescale 1ns/10ps

`include "defines.v"

module zet_cache_line
(
	input clk,
	input rst,

	input [15:0] wb_data,
	input [4:0] shift,
	input we_data,
	input we_shift,

	output cache_not_full,
	output [4:0] bytes_in_cache_line,
	output [(`CACHE_LINE_SIZE*8)-1:0] cache_line
);

	reg [(`CACHE_LINE_SIZE * 8)-1:0] __cache_line;
	reg [4:0] __bytes_in_cache_line;
	wire __cache_line_not_full;

	assign bytes_in_cache_line = __bytes_in_cache_line;
	assign cache_line = __cache_line;
	assign cache_not_full = (bytes_in_cache_line < (5'd16));

	always @(posedge clk)
	begin
		if(rst)
		begin
			__bytes_in_cache_line <= 5'h0;
			__cache_line <= `CACHE_LINE_SIZE'h0;
		end

		else if(we_shift)
		begin
			__bytes_in_cache_line <= (__bytes_in_cache_line - shift);
			__cache_line <= (__cache_line >> (shift * 8));
		end

		else if(we_data)
		begin
/*

			__cache_line[7:0]		<= (__bytes_in_cache_line == 0) ? wb_data : __cache_line[7:0];
			__cache_line[15:8]	<= (__bytes_in_cache_line == 1) ? wb_data : __cache_line[15:8];
			__cache_line[23:16]	<= (__bytes_in_cache_line == 2) ? wb_data : __cache_line[23:16];
			__cache_line[31:24]	<= (__bytes_in_cache_line == 3) ? wb_data : __cache_line[31:24];
			__cache_line[39:32]	<= (__bytes_in_cache_line == 4) ? wb_data : __cache_line[39:32];
			__cache_line[47:40]	<= (__bytes_in_cache_line == 5) ? wb_data : __cache_line[47:40];
			__cache_line[55:48]	<= (__bytes_in_cache_line == 6) ? wb_data : __cache_line[55:48];
			__cache_line[63:56]	<= (__bytes_in_cache_line == 7) ? wb_data : __cache_line[63:56];
			__cache_line[71:64]	<= (__bytes_in_cache_line == 8) ? wb_data : __cache_line[71:64];
			__cache_line[71:64]	<= (__bytes_in_cache_line == 9) ? wb_data : __cache_line[79:72];
			__cache_line[71:64]	<= (__bytes_in_cache_line == 10) ? wb_data : __cache_line[87:80];
			__cache_line[71:64]	<= (__bytes_in_cache_line == 11) ? wb_data : __cache_line[95:88];
			__cache_line[71:64]	<= (__bytes_in_cache_line == 12) ? wb_data : __cache_line[103:96];
			__cache_line[71:64]	<= (__bytes_in_cache_line == 13) ? wb_data : __cache_line[111:104];
			__cache_line[71:64]	<= (__bytes_in_cache_line == 14) ? wb_data : __cache_line[119:112];
			__cache_line[71:64]	<= (__bytes_in_cache_line == 15) ? wb_data : __cache_line[127:120];

			__bytes_in_cache_line <= (__bytes_in_cache_line + 1);

*/

			__cache_line[15:0]		<= (__bytes_in_cache_line == 0) ? wb_data : __cache_line[15:0];
			__cache_line[31:16]	<= (__bytes_in_cache_line == 2) ? wb_data : __cache_line[31:16];
			__cache_line[47:32]	<= (__bytes_in_cache_line == 4) ? wb_data : __cache_line[47:32];
			__cache_line[63:48]	<= (__bytes_in_cache_line == 6) ? wb_data : __cache_line[63:48];
			__cache_line[79:64]	<= (__bytes_in_cache_line == 8) ? wb_data : __cache_line[79:64];
			__cache_line[95:80]	<= (__bytes_in_cache_line == 10) ? wb_data : __cache_line[95:80];
			__cache_line[111:96]	<= (__bytes_in_cache_line == 12) ? wb_data : __cache_line[111:96];
			__cache_line[127:112]	<= (__bytes_in_cache_line == 14) ? wb_data : __cache_line[127:112];

			__bytes_in_cache_line <= (__bytes_in_cache_line + 2);

		end
	end
endmodule

